Field
The disclosed technology generally relates to semiconductors, and more particularly to a method for forming a junction field effect transistor (JFET).
Description of the Related Technology
Fabrication of semiconductor devices, e.g., transistors, involves various processes including deposition, diffusion, doping, lithography and etch, among other processes. Likewise, fabrication of a junction field effect transistor (JFET) involves a number of processes, including, e.g., creation of a well, formation of a source, a drain and a gate by dopant implantation, and formation of contacts, among other processes. At least some of these processes follow a patterning process using a lithographic mask, for example, for covering the substrate except for regions into which dopants are subsequently implanted to form the source and drain. The number of masks used in the fabrication depends, e.g., on the complexity and size of the JFET, and/or the type of electronic chip in which the JFET is being integrated.
In many integrated circuit (IC) fabrication process flows, it is becoming increasingly desirable to reduce or minimize the number of masks used, whose number is inversely proportional to the processing cost. One example area of such fabrication process flows includes fabrication process flows for integrating interposer chips. Interposer chips refer to silicon substrates used as an interface between a carrier substrate and one or more ICs. Interposers play an important role in present day IC packaging solutions. Some interposers are passive interposers, which carry the ICs and connect them to the carrier substrate using through silicon via (TSV) connections. Some interposers are active interposers, which are provided with a number of active devices produced on the interposer by a front-end-of-line type process. Integrating more active devices on the interposer is, however, increasingly difficult without increasing the complexity and cost of the process steps applied for this purpose. Thus, there is a need for fabrication process flows for integrating interposer chips using reduced number of masks.